The invention relates to a DC—DC converter for switching a semiconductor switch device to convert a DC voltage to a certain level and for supplying the DC voltage to a load. Specifically, the invention relates to a DC—DC converter that reduces a switching loss of the semiconductor switch device even when an output voltage fluctuates.
A DC—DC converter switches a semiconductor switch device to convert a DC voltage, and conducts feedback control to maintain an output voltage supplied to a load at a certain value. In this case, when a load current becomes below 20 to 30% of a rated current, the switch device converts the voltage through the switching with extremely low efficiency. In order to prevent the voltage conversion efficiency from lowering at a low load current, in a known method, a switching frequency is lowered according to the decease in the load current to reduce a loss associated with the switching of the switch device.
Conventional feedback control methods for the DC—DC converter include pulse width modulation (hereinafter referred to as “PWM”) and pulse frequency modulation (hereinafter referred to as “PFM”). Japanese Patent Publications (Kokai) No. 11-155281, No. 2001-112251, and No. 2001-157446 have disclosed DC—DC converters employing, in addition to the PWM control mode, the PFM control mode in which the switching frequency is lowered in response to the decrease in the load current to maintain high conversion efficiency in a wide load range.
The PWM control mode for the DC—DC converter will be described next. FIG. 29 is a block circuit diagram of a step-down DC—DC converter with the PWM control mode.
In the step-down DC—DC converter, an input power supply voltage Vin is converted to a certain voltage level and is supplied to a load LOAD. The step-down DC—DC converter includes an error amplifier Amp1, a capacitor C1 for phase compensation, a resistance R1 for phase compensation, a feedback resistance R2, a feedback resistance R3, an oscillator circuit OSC2, a comparator Cmp1 for pulse width modulation, a p-channel output transistor (MOSFET) P1, an n-channel output transistor (MOSFET) N1, a choke coil L, a driver circuit Dr1, a driver circuit Dr2, and a smoothing capacitor Cout.
In the step-down DC—DC converter with the PWM control mode, a resistance divides an output voltage signal Vout to obtain a feedback signal Vfb, and it is controlled so that the feedback signal Vfb is equal to an output voltage control signal Vcont for determining the output voltage signal Vout. For example, when the feedback resistance R1 and the feedback resistance R2 for dividing the output voltage signal Vout have the same value, the output voltage signal Vout is twice as high as the output voltage control signal Vcont.
The output voltage control signal Vcont is connected to a positive input terminal of the error amplifier (operational amplifier) Amp1. The feedback signal Vfb is connected to a negative input terminal of the error amplifier Amp1. The error amplifier Amp1 constitutes an integration circuit using the phase compensation resistance R1 and the phase compensation capacitor C1. An error amplifier output signal Verr from the error amplifier Amp1 and a triangular wave signal Vosc2 from the oscillator circuit OSC2 are inputted to the comparator Cmp1 for pulse width modulation.
A source of the p-channel transistor P1 is connected to the input power supply voltage Vin and a drain of the p-channel transistor P1 is connected to the choke coil L. The driver circuit Dr1 drives a gate of the p-channel transistor P1. The n-channel transistor N1 is connected to the ground potential GND and the choke coil L. The driver circuit Dr2 drives a gate of the n-channel transistor N1. The output voltage signal Vout is converted to the DC voltage by the choke coil L and the smoothing capacitor Cout, and is supplied to the load LOAD.
The PMW control mode of the DC—DC converter will be described next. The oscillator circuit OSC2 oscillates at a predetermined frequency and outputs a triangular wave signal Vosc2. The triangular wave signal Vosc2 and the error amplifier output signal Verr are inputted to the comparator Cmp1 for pulse width modulation. The comparator Cmp1 outputs a pulse-width-modulation signal Vcmp to the driver circuits Dr1 and Dr2. When the signal Vcmp is “Low”, the p-channel transistor P1 is switched on. When the signal Vcmp is “High”, the n-channel transistor N1 is switched on. The driver circuits Dr1 and Dr2 adjust timings thereof so that the p-channel transistor P1 and the n-channel transistor N1 are not switched on at the same time to prevent a through current from flowing from the input power supply voltage Vin to the ground potential GND.
When the p-channel transistor P1 is on, electric charges flow from the input power supply voltage Vin to the smoothing capacitor Cout via the choke coil L, so that a current flowing through the choke coil L increases. When the n-channel transistor N1 is switched on, electric charges flow from the ground potential GND to the smoothing capacitor Cout, so that the current flowing through the choke coil L decreases. The feedback resistance R2 and the feedback resistance R3 divide the output voltage signal Vout to generate the feedback signal Vfb. The feedback signal Vfb is inputted to the error amplifier Amp1 together with the output voltage control signal Vcont, and the feedback control is conducted so that the feedback signal Vfb becomes equal to the output voltage control signal Vcont.
The feedback control will be described below with reference to FIGS. 30(a) and 30(b). FIGS. 30(a) and 30(b) are views showing operational waveforms in the PWM control mode of the step-down DC—DC converter.
A period of time when the p-channel transistor P1 is on is defined as ton, and a period of time when the n-channel transistor N1 is on is defined as toff. In this case, a ratio of the output voltage signal Vout and the input power supply voltage Vin is given by the following expression.Vout/Vin=ton/(ton+toff)In the following, the ratio, ton/(ton+toff), will be referred to as a duty ratio.
A case that the error amplifier output signal Verr drops from a state shown in FIG. 30(a) to a state shown in FIG. 30(b) will be considered. In a case that the output voltage signal Vout increases when a current flowing in the load LOAD (hereinafter referred to as the “load current”) changes, the feedback signal Vfb obtained by dividing the output voltage signal Vout by the resistance also increases. As a result, the error amplifier output signal Verr drops. Accordingly, the ON-period ton of the p-channel transistor P1 decreases and the ON-period toff of the n-channel transistor N1 increases to lower a voltage of the output voltage signal Vout. The feedback control of the DC—DC converter is performed as described above, so that the output voltage signal Vout remains constant even when the load current changes.
The PFM control mode will be described next. FIG. 31 is a block circuit diagram of a step-down DC—DC converter with the PFM control mode. As shown in FIG. 31, the step-down DC—DC converter includes an error amplifier Amp1, a capacitor C1 for phase compensation, a resistance R1 for phase compensation, a feedback resistance R2, a feedback resistance R3, an oscillator circuit OSC3, a comparator Cmp1 for pulse width modulation, a one-shot circuit One-shot, a p-channel output transistor (MOSFET) P1, a diode D1, a choke coil L, a driver circuit Dr1, and a smoothing capacitor Cout.
In the same manner as the circuit shown in FIG. 29, a resistance divides an output voltage signal Vout to obtain a feedback signal Vfb, and it is controlled so that the feedback signal Vfb is equal to an output voltage control signal Vcont supplied from outside. For example, when the feedback resistance R1 and the feedback resistance R2 for dividing the output voltage signal Vout have the same value, the output voltage signal Vout is twice as high as the output voltage control signal Vcont.
The output voltage control signal Vcont is connected to the positive input terminal of the error amplifier Amp1. The feedback signal Vfb is connected to the negative input terminal of the error amplifier Amp1. The error amplifier Amp1 constitutes an integration circuit using the phase compensation resistance R1 and the phase compensation capacitor C1. The error amplifier output signal Verr from the error amplifier Amp1 and the triangular wave signal Vosc3 from the oscillator circuit OSC3 are inputted to the comparator Cmp1 for pulse width modulation. The error amplifier output signal Verr is inputted also to the oscillator circuit OSC3.
The source of the p-channel transistor P1 is connected to the input power supply voltage Vin and the drain of the p-channel transistor P1 to the choke coil L. The driver circuit Dr1 drives the gate of the p-channel transistor P1. A pulse signal Vpls outputted from the one-shot circuit One-shot is used for the gate signal of the p-channel transistor P1. The one-shot circuit One-shot generates the pulse signal Vpls having a certain time width using a transitional point of the pulse-width-modulation signal Vcmp as a trigger. The feedback diode D1 is connected between the ground potential GND and the choke coil L. The choke coil L and the smoothing capacitor Cout convert the output voltage signal Vout to the DC voltage, and the output voltage signal Vout is supplied to the load LOAD.
When the voltage of the output voltage control signal Vcont increases, the error amplifier output signal Verr increases, and an oscillation frequency of the triangular wave signal Vosc3 outputted from the oscillator circuit OSC3 increases. As a result, the switching frequency of the p-channel transistor P1 increases, the current flowing to the smoothing capacitor Cout through the choke coil L increases, and the output voltage signal Vout increases. Thus, in the PFM control mode, the voltage of the output voltage signal Vout is controlled based on the voltage of the output voltage control signal Vcont through the feedback control.
FIGS. 32(a) to 32(d) are views showing waveforms in the PFM control mode of the DC—DC converter.
FIG. 32(a) shows a waveform representing the error amplifier output signal Verr and the triangular wave signal Vosc3 inputted to the comparator Cmp1 for the pulse width modulation. The oscillator circuit OSC3 outputs the triangular wave signal Vosc3 having a frequency corresponding to the error amplifier output signal Verr.
FIG. 32(b) shows a waveform representing the pulse-width-modulation signal Vcmp. The comparator for the pulse width modulation Cmp1 compares the error amplifier output signal Verr with the triangular wave signal Vosc3, and outputs the pulse-width-modulation signal Vcmp to the one-shot circuit One-shot.
FIG. 32(c) shows a waveform representing the pulse signal Vpls outputted from the one-shot circuit One-shot. The pulse signal Vpls, triggered by the transitional point of the pulse-width-modulation signal Vcmp and having a certain time width tpluse, is outputted to the driver circuit Dr1. Since the p-channel transistor P1 is switched on by the driver circuit Dr1 during the “Low” period of the pulse signal Vpls, a current flows from the input power supply voltage Vin into the choke coil L via the p-channel transistor P1.
FIG. 32(d) shows a waveform representing the current flowing through the choke coil L. The coil current IL increases from 0 at a slope of (Vin−Vout)/L relative to time after the p-channel transistor P1 is switched on. After the p-channel transistor P1 is switched off, a current flows from the choke coil L to the ground potential GND via the feedback diode D1. The current decreases at a slope of Vout/L relative to time.
The feedback resistance R2 and the feedback resistance R3 divide the output voltage signal Vout to generate the feedback signal Vfb. The feedback signal Vfb is inputted together with the output voltage control signal Vcont to the error amplifier Amp1. As a result, the output voltage control signal Vcont is controlled to be equal to the feedback signal Vfb through the feedback control.
In an actual case, the output voltage signal Vout is determined by a sum of the current flowing out from the smoothing capacitor Cout to the load LOAD and the current flowing into the smoothing capacitor Cout via the choke coil L. The feedback control is conducted so that these currents have the same value. In other words, the output voltage signal Vout increases when the load current decreases, and the feedback signal Vfb obtained by dividing the output voltage signal Vout by the resistance also increases. Therefore, when the error amplifier output signal Verr decrease, the oscillation frequency of the triangular wave signal Vosc3 decreases. As a result, the switching frequency of the p-channel transistor P1 decreases, and the current flowing into the smoothing capacitor Cout via the choke coil L decreases.
Thus, the DC—DC converter with the PFM control mode performs the feedback control to maintain the output voltage signal Vout at a certain value even when the load current changes.
Recently, a demand for changing the output voltage at a high speed when the DC—DC converter is in use has been increased. The conventional DC—DC converter generates a certain output voltage based on a fixed reference voltage. In contrast, instead of the conventional fixed reference voltage, it has been desired to provide a circuit configuration that changes the output voltage of the DC—DC converter based on, for example, a variable reference voltage supplied from outside.
For example, in a power amplifier used for a portable telephone set with the W-CDMA system, it is necessary to reduce a power consumption of the power supply incorporated in the portable telephone set. To this end, when the portable telephone set is positioned near the base station transmitting and receiving the radio waves, the transmission power is suppressed. In other words, the power supply voltage supplied to the power amplifier is changed corresponding to the power necessary for transmission.
In order to stably control the output voltage corresponding to a wide range of input voltages and load variations, Japanese Patent Publication (Kokai) No. 2001-258245 has disclosed a DC—DC converter in which a primary side driver circuit is switched between the time ratio modulation mode and the frequency modulation mode to follow the wide input voltage variations and the wide load variations.
In the integrated circuit shown in FIG. 29 formed of the error amplifier Amp1, the resistance R1 and the capacitor C1, Japanese Patent Publication No. 2002-78326 has described that when the output voltage control signal Vcont changes stepwise, the change directly affects an output of the error amplifier Amp1, thereby causing an overshoot.
As described above, in the DC—DC converter with the function of switching between the PWM control mode and the PFM control mode, it has been known to be possible to maintain the output voltage signal Vout at a certain value while exhibiting high conversion efficiency in a wide load range. However, in a case that the output voltage control signal Vcont inputted as a reference voltage changes rapidly under a light load, when the DC—DC converter is operated in the PFM mode, the output voltage signal Vout responses to the rapid change very slowly.
The response characteristic of the output voltage signal Vout will be further described next. FIGS. 33(a) to 33(e) are views showing waveforms describing a change in the output voltage signal Vout under the PFM control mode.
As shown in FIG. 33(a), the output voltage control signal Vcont increases at a time t1 and decreases at a time t3. According to the change in the output voltage control signal Vcont described above, the output voltage signal Vout increases from a potential Vout1 to a potential Vout2 for a period of time Tr1, and decreases from the potential Vout2 to the potential Vout1 for a period of time Tf1 as shown in FIG. 33(b).
A current of the output capacitance formed by the smoothing capacitor Cout is a sum of the load current and a current for changing the electric charge of the smoothing capacitor according to the change in the output voltage signal Vout. For the sake of the explanation, the load current is assumed to be constant as shown in FIG. 33(c) irrespective of the output voltage signal Vout. As shown in FIG. 33(d), the current flows in and out to change the electric charges in the smoothing capacitor Cout.
In the PFM control mode, as shown in FIG. 33(e), the change in the switching frequency controls the change in the current. Therefore, in the PFM control mode, it is difficult to follow the rapid change like the case in the PWM control mode.
In the portable telephone set with the W-CDMA system, it is necessary to change the power supply voltage in several tens of microseconds. It is not possible to flow the current in the negative direction when the voltage decreases (during the period between the time t3 and the time T4). The electric charges in the smoothing capacitor Cout can be discharged only by flowing the current to the load LOAD. When the load current is small, the period Tf1 necessary for decreasing the output voltage signal Vout from the potential Vout2 to the potential Vout1 takes too long to meet the requirement of several tens of microseconds described above.
In view of the problems described above, an object of the invention is to provide a DC—DC converter in which high efficiency in a wide load range is maintained and the response of the output voltage signal is not deteriorated under the light load condition.
It is also an object of the invention to provide a DC—DC converter in which overshooting of the output voltage signal does not occur even when the output voltage control signal changes stepwise.
A further object of the invention is to provide a DC—DC converter in which undershooting and overshooting are suppressed during the switching between the PWM control mode and the PFM control mode to minimize absolute values of the overshooting and the undershooting, and it is possible to shorten periods of the overshooting and the undershooting.
Further objects and advantages of the invention will be apparent from the following description of the invention.